High speed memory devices can play an important role in high speed applications, including but not limited to circuits for communication systems and networks. Conventionally, static random access memories (SRAM) fulfill high speed access roles. SRAMs can store data in a static fashion (i.e., do not have to be refreshed), typically with a latching structure.
A conventional SRAM sensing operation typically includes: discharging one bit line of a bit line pair (to thereby generate a small differential signal across a bit line pair); amplifying the small signal with sense amplifier circuits; and equalizing the bit lines and sense amplifier circuits for a next sensing operation.
At very high speeds of operation (e.g., 3 GHz clock speed or faster), it can be very difficult to accomplish the above sensing operation tasks within a single clock period.
Various conventional approaches to improving sensing operation speeds are known. The speed at which a bit line can discharge can be limited by a capacitance of the bit line. Reducing the number of memory cells per bit line can reduce bit line capacitance, but at an undesirable increase in device size. The speed at which a bit line can discharge can also be limited by a memory cell current (i.e., current drawn by memory cell when connected to the bit line). However, even the smallest increases in memory cell can greatly impact a device (as there can be millions of such cells in the memory device). Reducing the number of memory cells per bit line can reduce bit line capacitance, but at an undesirable increase in device size.
A sensing speed for a sense amplifier can be increased by reducing a mismatch at differential inputs of a sense amplifier (SA). However, reductions in mismatch can require increased circuit area, again undesirably increasing device size. Further, increasing SA input area can also increase capacitance, working against sensing speed.
FIGS. 11A and 11B show one conventional approach to sensing operations in a memory device. FIG. 11A shows a conventional memory device 1100 having a bit lines 1111, a column MUX 1103, first switch circuits 1105, a pre-amplifier (or first SA) 1107, second switch circuits 1113, and a SA 1109.
FIG. 11B is a timing diagram showing a conventional sense operation for memory device 1100. FIG. 11B shows a number of waveforms: CLK shows a clock signal that can control operations of the conventional memory device; BL/BLB shows responses of bit line pairs; PA_OUT shows outputs of pre-amplifier 1107; and SA_OUT shows outputs of SA 1109.
At about time to, a memory cell can be connected to a bit line pair. One bit line can discharge through the memory cell, resulting in the bit lines “splitting” (developing a very small differential voltage). After time t0, first switch circuits 1105 can connect the bit line pair to pre-amplifier 1107.
At about time t1, pre-amplifier 1107 can be activated providing a fast, but small amplification of the differential signal PA_OUT. Also, about this time, the memory cell can be disconnected from the bit line pair, and the bit line pair can be equalized.
At about time t2, second switch circuits 1113 can connect sense amplifier 1109 to an output of pre-amplifier 1107, and sense amplifier 1109 can be activated, amplifying the small signal to generate a larger output signal SA_OUT.
The conventional memory device 1100 can provide needed access speeds. However, the use of two sensing circuits (1107 and 1109) can adversely contribute to increased device size.